Physical Design Technical Manager

4ASICs is looking for an Physical Design Technical Manager to build and lead our new Physical Design team. This role is suitable for a hands-on technical leader with strong Physical Design experience, successful tape-outs, and exposure to advanced TSMC FinFET technology nodes.

The Opportunity 

Build Something That Matters. 4ASICs is expanding its Digital Back-End Design capability and is seeking an experienced, hands-on Physical Design leader to establish and grow a new team. This high-impact role combines end-to-end technical execution, team development, methodology ownership, and customer engagement across international semiconductor projects. 

Key Responsibilities 

Technical Leadership & Execution: Lead Digital Physical Design implementation from synthesized netlist through GDSII signoff across multiple projects. 

Design Closure & Signoff: Drive floorplanning, power planning, placement, CTS, routing, timing closure, power optimization, signal integrity, IR drop, EM, and physical verification. 

Team Building & Mentorship: Recruit, mentor, and develop a high-performing Physical Design team, with clear training plans, engineering standards, and technical reviews. 

Methodology & Automation: Define, improve, and automate Physical Design methodologies and EDA flows using Tcl, Python, or similar scripting languages. 

Customer & Project Leadership: Serve as the primary technical interface for international customers, lead design reviews, and ensure project quality, schedule, and delivery. 

Business Support: Provide technical input for customer discussions, project scoping, proposals, and pre-sales activities. 

Cross-Functional Collaboration: Work closely with RTL, STA, DFT, Verification, and Analog/Mixed-Signal teams to resolve design issues and achieve successful tape-outs. 

Requirements 

Education: Bachelor's or Master's Degree in Electrical/Electronics Engineering, Computer Engineering, Microelectronics, or a related discipline. 

Experience: At least 8 years of hands-on Digital Physical Design experience, including successful tape-outs and technical team leadership. Candidates with strong technical and keen to move to leadership position or roles are strongly encouraged to apply. 

Advanced Nodes: Strong practical experience with TSMC FinFET technologies, preferably from 16nm down to 3nm or smaller advanced nodes. 

Core Expertise: Strong knowledge of RTL-to-GDSII implementation, floorplanning, power planning, placement, CTS, routing, ECO, MMMC, timing closure, DRC/LVS, signal integrity, IR drop, and EM. 

EDA Tools: Experience with Cadence Innovus, Tempus and Voltus; Synopsys ICC2 or Fusion Compiler and PrimeTime; and Siemens Calibre, or equivalent industry tools. 

Leadership & Communication: Demonstrated ability to guide engineers, solve complex implementation issues, and communicate effectively with international customers in business English. 

Automation: Working knowledge of Linux and scripting using Tcl, Python, Perl, or shell. 

What We're Looking For  

Hands-On Technical Leader: Able to remain technically engaged while setting direction and driving execution. 

Team Builder: Motivated to mentor engineers and build a sustainable Physical Design capability from the ground up. 

Customer-Oriented Professional: Confident in technical discussions, design reviews, and cross-cultural collaboration. 

Ownership Mindset: Strong problem-solving, project leadership, and commitment to quality and delivery. 

Why Join 4ASICs? 

• Build and shape a new Digital Back-End Design team. 
• Work with international (Europe) semiconductor customers.
• Work across technology nodes, foundries, and diverse IC applications. 
• Collaborate with experienced Analog, Mixed-Signal, RF, and Digital teams of international design companies. 
• Grow beyond project execution into strategic technical leadership, customer engagement, and business expansion. 

Interested candidates please submit your application through Jobstore.com